The present invention relates to a semiconductor device and more particularly to a flash memory device including a high-voltage switch circuit which can increase the switching operating speed.
A high voltage semiconductor memory device includes a high-voltage switch circuit. The high-voltage switch circuit supplies or cuts off the high voltage to an internal circuit requiring the high voltage in response to a switch control voltage.
FIG. 1 is a circuit diagram of a high-voltage switch circuit in the related art. A high-voltage switch circuit 10 includes an enable control circuit 11, a high voltage switch 12, and a boosting circuit 13. The enable control circuit 11 and the high voltage switch 12 may be implemented using a high voltage NMOS transistor. Hereinafter, it is assumed that each of the enable control circuit 11 and the high voltage switch 12 is an NMOS transistor. The boosting circuit 13 includes NMOS transistors N1, N2 and capacitors C1, C2.
The operation process of the high-voltage switch circuit 10 will be described in short below. If an enable signal EN is set to VCC, the NMOS transistor 11 supplies an output node OUT with VCC−Vth1, where Vth1 is the threshold voltage of the NMOS transistor 11. As a result, a voltage VCC−Vth1 is generated by the switch control voltage VO onto the output node OUT.
The NMOS transistor N1 is turned on in response to the switch control voltage VO and outputs an internal output voltage VINT=VCC−Vth1−Vth2, where Vth2 is the threshold voltage of the NMOS transistor N1. At this time, a logic high clock signal CLK is input to the capacitor C1. Consequently, the internal output voltage VINT can be expressed by the following Equation.
                    VINT        =                                            (                              1                +                                                                            C                      c                                        ⁢                    1                                                                                                      C                        c                                            ⁢                      1                                        +                                                                  C                        s                                            ⁢                      1                                                                                  )                        ⁢            VCC                    -                      Vth            ⁢                                                  ⁢            1                    -                      Vth            ⁢                                                  ⁢            2                                              [                  Equation          ⁢                                          ⁢          1                ]            
(where Cc1 is capacitance of C1 and Cs1 is capacitance of CE)
In Equation 1, CE denotes a parasitic capacitor existing in the node A. When the clock signal CLK goes high, an inverted clock signal CLKB goes low (e.g., a voltage VSS). Thereafter, the diode-connected NMOS transistor N2 is turned on in response to the internal output voltage VINT and outputs the internal output voltage VINT to the output node OUT. The NMOS transistor N2 may be implemented using a low-voltage transistor. Accordingly, since the threshold voltage of the NMOS transistor N2 is significantly smaller than the threshold voltage Vth2 of the NMOS transistor N1, the voltage drop in the internal output voltage VINT by the NMOS transistor N2 can be ignored.
Meanwhile, the inverted clock signal CLKB is input to the capacitor C2 as logic high (VCC). As a result, the switch control voltage VO is boosted by the internal output voltage VINT and the voltage VCC of the inverted clock signal CLKB, as represented by the following Equation.
                    VO        =                  VINT          +                                    (                                                                    C                    c                                    ⁢                  2                                                                                            C                      c                                        ⁢                    2                                    +                                                            C                      s                                        ⁢                    2                                                              )                        ⁢            VCC                                              [                  Equation          ⁢                                          ⁢          2                ]            
(where Cc2 is capacitance of C2 and Cs2 is capacitance of CF)
In Equation 2, CF is a parasitic capacitor existing in the output node OUT. When the inverted clock signal CLKB goes high, the clock signal CLK goes low. Thereafter, an increased switch control voltage VO is input to the gate of the NMOS transistor N1 again. The high-voltage switch circuit 10 then repeats the above-mentioned operations until the switch control voltage VO is boosted to a voltage VPP+Vth3, where VPP>>VCC and Vth3 is the threshold voltage of the NMOS transistor 12. When VO reaches VPP+Vth3 the NMOS transistor 12 is fully turned on and there is no voltage drop across NMOS transistor 12 when VPP is output to high-voltage HVOUT.
The NMOS transistor N1 included in the boosting circuit 13 is implemented using a high-voltage transistor since it receives the high voltage VPP. However, the threshold voltage of the high-voltage transistor is much higher than that of the low-voltage transistor. Accordingly, if the NMOS transistor N1 is implemented with the high-voltage transistor, a voltage dropped by the NMOS transistor N1 is much higher than that dropped by the low-voltage transistor.
If a voltage dropped by the NMOS transistor N1 is increased as described above, the internal output voltage VINT decreases and the boosting speed of the switch control voltage VO is decreased. As a result, a time T2 from when the enable signal EN is enabled to when the high-voltage switch circuit 10 (i.e., the NMOS transistor 12) is fully turned on is increased.
In addition, if the voltage VPP input to the drain of the NMOS transistor N1 increases, there is a possibility that the switch control voltage VO may not be normally boosted because the threshold voltages of the NMOS transistors N1, N2 are excessively increased due to the body effect of the NMOS transistors N1, N2. In this case, the high-voltage switch circuit 10 cannot perform the switching operation normally.
Furthermore, in the high-voltage switch circuit 10, the switch control voltage VO of the output node OUT is boosted directly by the inverted clock signal CLKB. Accordingly, as shown in FIG. 2, the switch control voltage VO includes noise components generated as the inverted clock signal CLKB is toggled. The noise components of the switch control voltage VO have a direct effect on the high-voltage HVOUT, and the high-voltage HVOUT also include the noise components as shown in FIG. 2.
Meanwhile, the amplitudes of the clock signal CLK and the inverted clock signal CLKB may be reduced in order to reduce the noise components of the high-voltage HVOUT. If the amplitudes of the clock signal CLK and the inverted clock signal CLKB are reduced, the boosting speed of the switch control voltage VO is decreased and in-turn the operating speed of the high-voltage switch circuit 10 is also decreased.